diff options
| author | Jan Kiszka <jan.kiszka@siemens.com> | 2009-05-02 00:29:37 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-05-22 10:50:34 -0500 |
| commit | 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (patch) | |
| tree | fff3d6f590833c0f894a6c7c300ab126b5259d95 /hw/ppc4xx_devs.c | |
| parent | 93102fd6010c68320bc9a008c8cf70cb4a36d4b9 (diff) | |
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.
Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ppc4xx_devs.c')
| -rw-r--r-- | hw/ppc4xx_devs.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index ddee8f6338..5c8d2734a0 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -60,7 +60,7 @@ CPUState *ppc4xx_init (const char *cpu_model, tb_clk->opaque = env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ - qemu_register_reset(&cpu_ppc_reset, env); + qemu_register_reset(&cpu_ppc_reset, 0, env); return env; } @@ -498,7 +498,7 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs, ppc_dcr_register(env, dcr_base + i, uic, &dcr_read_uic, &dcr_write_uic); } - qemu_register_reset(ppcuic_reset, uic); + qemu_register_reset(ppcuic_reset, 0, uic); ppcuic_reset(uic); return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ); @@ -834,7 +834,7 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks, memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t)); sdram_reset(sdram); - qemu_register_reset(&sdram_reset, sdram); + qemu_register_reset(&sdram_reset, 0, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, |