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authorAvi Kivity <avi@redhat.com>2011-08-04 15:55:30 +0300
committerAvi Kivity <avi@redhat.com>2011-08-25 10:56:33 +0300
commitc8a50e596c8eeb41bf5718df5bad6be4080f40c7 (patch)
tree589bfb006ec42863a518debd4775d88a3abfe185 /hw/ppc405_boards.c
parenta1807ef2954d3ddbf9a9bca3949bd0c69fd45a0e (diff)
pflash_cfi01/pflash_cfi02: convert to memory API
cfi02 is annoying in that is ignores some address bits; we probably want explicit support in the memory API for that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'hw/ppc405_boards.c')
-rw-r--r--hw/ppc405_boards.c63
1 files changed, 35 insertions, 28 deletions
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index dec165e40f..1eb807c4c1 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -32,6 +32,7 @@
#include "qemu-log.h"
#include "loader.h"
#include "blockdev.h"
+#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024)
@@ -181,7 +182,9 @@ static void ref405ep_init (ram_addr_t ram_size,
ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
- ram_addr_t sram_offset, bios_offset, bdloc;
+ ram_addr_t sram_offset, bdloc;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
@@ -224,18 +227,18 @@ static void ref405ep_init (ram_addr_t ram_size,
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv);
- bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
+ memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
+ NULL, "ef405ep.bios", bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr %lx '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
} else
#endif
@@ -243,12 +246,12 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
- bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@@ -259,8 +262,9 @@ static void ref405ep_init (ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(address_space_mem, (uint32_t)(-bios_size),
+ bios);
}
/* Register FPGA */
#ifdef DEBUG_BOARD_INIT
@@ -507,7 +511,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
{
char *filename;
qemu_irq *pic;
- ram_addr_t bios_offset;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *bios = g_new(MemoryRegion, 1);
+ MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
@@ -544,17 +550,17 @@ static void taihu_405ep_init(ram_addr_t ram_size,
/* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
+ memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
+ NULL, "taihu_405ep.bios", bios_size);
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr %lx '%s' %d\n",
- fl_idx, bios_size, bios_offset, -bios_size,
+ " at addr %lx '%s' %d\n",
+ fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
- pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
+ pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
} else
#endif
@@ -564,10 +570,10 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#endif
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
+ memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
- bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
+ bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@@ -578,8 +584,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
- cpu_register_physical_memory((uint32_t)(-bios_size),
- bios_size, bios_offset | IO_MEM_ROM);
+ memory_region_set_readonly(bios, true);
+ memory_region_add_subregion(address_space_mem,
+ (uint32_t)(-bios_size), bios);
}
/* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@@ -590,15 +597,15 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
- " at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
- fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
+ " at addr " TARGET_FMT_lx " '%s'\n",
+ fl_idx, bios_size, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
- bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
- pflash_cfi02_register(0xfc000000, bios_offset,
+ memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
+ NULL, "taihu_405ep.flash", bios_size);
+ pflash_cfi02_register(0xfc000000, flash,
dinfo->bdrv, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
fl_idx++;
}
/* Register CLPD & LCD display */