diff options
author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-16 23:45:36 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-04-16 23:45:36 +0000 |
commit | 4fbd24ba35ce80b23253002116d5a90df6d25b2c (patch) | |
tree | 4109e93fdd15090405dee9c090663209385fd6dd /hw/ppc405_boards.c | |
parent | 6725070d8dba75fefb9f852c64239a988ef42caa (diff) |
Emulate address wrap in CFI02 chips mapping (Jan Kiszka).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4219 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/ppc405_boards.c')
-rw-r--r-- | hw/ppc405_boards.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c index ca986a02c3..b1a15e8a84 100644 --- a/hw/ppc405_boards.c +++ b/hw/ppc405_boards.c @@ -235,8 +235,8 @@ static void ref405ep_init (int ram_size, int vga_ram_size, bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, - drives_table[index].bdrv, 65536, fl_sectors, 2, - 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + drives_table[index].bdrv, 65536, fl_sectors, 1, + 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); fl_idx++; } else #endif @@ -552,8 +552,8 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size, bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); #endif pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, - drives_table[index].bdrv, 65536, fl_sectors, 4, - 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + drives_table[index].bdrv, 65536, fl_sectors, 1, + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); fl_idx++; } else #endif @@ -588,8 +588,8 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size, bdrv_get_device_name(drives_table[index].bdrv)); #endif pflash_cfi02_register(0xfc000000, bios_offset, - drives_table[index].bdrv, 65536, fl_sectors, 4, - 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); + drives_table[index].bdrv, 65536, fl_sectors, 1, + 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); fl_idx++; } /* Register CLPD & LCD display */ |