qemu: clean up target page usage in msix

Since cpu_register_phys_memory does not require size to be a multiple of
target page size, simply make msix page size 0x1000.  Do this in msix,
reverting part of 5e520a7d500ec2569d22d80f9ef4272a34cb3c80, as we no
longer have to pass target page around.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

1 files changed, 0 insertions, 6 deletions

diff --git a/hw/pci.h b/hw/pci.h
index d67c9f3d26..f3a034b356 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -213,12 +213,6 @@ struct PCIDevice {
     uint32_t msix_bar_size;
     /* Version id needed for VMState */
     int32_t version_id;
-    /* How much space does an MSIX table need. */
-    /* The spec requires giving the table structure
-     * a 4K aligned region all by itself. Align it to
-     * target pages so that drivers can do passthrough
-     * on the rest of the region. */
-    target_phys_addr_t msix_page_size;
 };
 
 PCIDevice *pci_register_device(PCIBus *bus, const char *name,