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authorScott Wood <scottwood@freescale.com>2012-12-21 16:15:45 +0000
committerAlexander Graf <agraf@suse.de>2013-01-07 17:37:10 +0100
commit72c1da2ca72af50e6536d0cd9c6db758f66cd7c2 (patch)
treec057f7b81e0ee455b7daf4a9cc35c57028b0652f /hw/openpic.c
parenteb4384278417297661663c54e01c0f0ffec0a9e3 (diff)
openpic/fsl: critical interrupts ignore mask before v4.1
Signed-off-by: Scott Wood <scottwood@freescale.com> [agraf: make bool :1] Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/openpic.c')
-rw-r--r--hw/openpic.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/hw/openpic.c b/hw/openpic.c
index 824b8fd2c2..ac5027a5a0 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -193,6 +193,7 @@ typedef struct IRQSource {
int last_cpu;
int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
int pending; /* TRUE if IRQ is pending */
+ bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
} IRQSource;
#define IVPR_MASK_SHIFT 31
@@ -389,7 +390,7 @@ static void openpic_update_irq(OpenPICState *opp, int n_IRQ)
DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
return;
}
- if (src->ivpr & IVPR_MASK_MASK) {
+ if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
/* Interrupt source is disabled */
DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
return;
@@ -529,6 +530,7 @@ static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val)
}
src->output = OPENPIC_OUTPUT_CINT;
+ src->nomask = true;
src->destmask = 0;
for (i = 0; i < opp->nb_cpus; i++) {
@@ -540,6 +542,7 @@ static inline void write_IRQreg_idr(OpenPICState *opp, int n_IRQ, uint32_t val)
}
} else {
src->output = OPENPIC_OUTPUT_INT;
+ src->nomask = false;
src->destmask = src->idr & normal_mask;
}
} else {