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authorAnthony Liguori <aliguori@us.ibm.com>2012-04-10 08:21:58 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-04-10 08:21:58 -0500
commit4e1957acc854b2f3f3068c75cef2a429f9b97011 (patch)
treecab3ca24ed0fc963cb693c0d440a9495a2cc47eb /hw/msix.h
parent6da25bd5e8355230b9562417e386728c31783002 (diff)
parentff71f2e8cacefae99179993204172bc65e4303df (diff)
Merge commit 'ff71f2e8cacefae99179993204172bc65e4303df' into staging
* commit 'ff71f2e8cacefae99179993204172bc65e4303df': (21 commits) rtl8139: do the network/host communication only in normal operating mode rtl8139: correctly check the opmode net: move compute_mcast_idx() to net.h rtl8139: support byte read to TxStatus registers rtl8139: remove unused marco rtl8139: limit transmission buffer size in c+ mode pci_regs: Add PCI_EXP_TYPE_PCIE_BRIDGE virtio-net: add DATA_VALID flag pci_bridge: upper 32 bit are long registers pci: fix bridge IO/BASE pcie: drop functionality moved to core pci: set memory type for memory behind the bridge pci: add standard bridge device slotid: add slot id capability shpc: standard hot plug controller pci_bridge: user-friendly default bus name pci: make another unused extern function static pci: don't export an internal function pci_regs: Fix value of PCI_EXP_TYPE_RC_EC. pci: Do not check if a bus exist in pci_parse_devaddr. ...
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