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authorIgor Mammedov <imammedo@redhat.com>2017-10-05 15:51:10 +0200
committerEduardo Habkost <ehabkost@redhat.com>2017-10-27 16:04:28 +0200
commita7519f2b39be7e584c9f5a3100f3842d314a5eb6 (patch)
treeeea94e6243977f4e75235ef81e5958c976323771 /hw/mips
parent81491c2846b7a818eb069dbc5f688537e382fc83 (diff)
mips: malta/boston: replace cpu_model with cpu_type
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1507211474-188400-37-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'hw/mips')
-rw-r--r--hw/mips/boston.c11
-rw-r--r--hw/mips/cps.c4
-rw-r--r--hw/mips/mips_malta.c33
3 files changed, 22 insertions, 26 deletions
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index e815be6a6c..1cb4b6aca2 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -437,7 +437,6 @@ static void boston_mach_init(MachineState *machine)
DeviceState *dev;
BostonState *s;
Error *err = NULL;
- const char *cpu_model;
MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg;
MemoryRegion *sys_mem = get_system_memory();
XilinxPCIEHost *pcie2;
@@ -453,25 +452,24 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
- cpu_model = machine->cpu_model ?: "I6400";
-
dev = qdev_create(NULL, TYPE_MIPS_BOSTON);
qdev_init_nofail(dev);
s = BOSTON(dev);
s->mach = machine;
- if (!cpu_supports_cps_smp(cpu_model)) {
+ if (!cpu_supports_cps_smp(machine->cpu_type)) {
error_report("Boston requires CPUs which support CPS");
exit(1);
}
- is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64);
+ is_64b = cpu_supports_isa(machine->cpu_type, ISA_MIPS64);
s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
- object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
+ object_property_set_str(OBJECT(s->cps), machine->cpu_type, "cpu-type",
+ &err);
object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
@@ -571,6 +569,7 @@ static void boston_mach_class_init(MachineClass *mc)
mc->block_default_type = IF_IDE;
mc->default_ram_size = 1 * G_BYTE;
mc->max_cpus = 16;
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
}
DEFINE_MACHINE("boston", boston_mach_class_init)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index fe5c630af6..4285d1964e 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
bool itu_present = false;
for (i = 0; i < s->num_vp; i++) {
- cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model));
+ cpu = MIPS_CPU(cpu_create(s->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@@ -160,7 +160,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
- DEFINE_PROP_STRING("cpu-model", MIPSCPSState, cpu_model),
+ DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index b6a58c7f21..ec6af4a277 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -923,7 +923,7 @@ static void main_cpu_reset(void *opaque)
}
}
-static void create_cpu_without_cps(const char *cpu_model,
+static void create_cpu_without_cps(const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
CPUMIPSState *env;
@@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_model,
int i;
for (i = 0; i < smp_cpus; i++) {
- cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
+ cpu = MIPS_CPU(cpu_create(cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
@@ -945,7 +945,7 @@ static void create_cpu_without_cps(const char *cpu_model,
*cbus_irq = env->irq[4];
}
-static void create_cps(MaltaState *s, const char *cpu_model,
+static void create_cps(MaltaState *s, const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
Error *err = NULL;
@@ -953,7 +953,7 @@ static void create_cps(MaltaState *s, const char *cpu_model,
s->cps = MIPS_CPS(object_new(TYPE_MIPS_CPS));
qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default());
- object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err);
+ object_property_set_str(OBJECT(s->cps), cpu_type, "cpu-type", &err);
object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err);
object_property_set_bool(OBJECT(s->cps), true, "realized", &err);
if (err != NULL) {
@@ -967,21 +967,13 @@ static void create_cps(MaltaState *s, const char *cpu_model,
*cbus_irq = NULL;
}
-static void create_cpu(MaltaState *s, const char *cpu_model,
- qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+static void mips_create_cpu(MaltaState *s, const char *cpu_type,
+ qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
- if (cpu_model == NULL) {
-#ifdef TARGET_MIPS64
- cpu_model = "20Kc";
-#else
- cpu_model = "24Kf";
-#endif
- }
-
- if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_model)) {
- create_cps(s, cpu_model, cbus_irq, i8259_irq);
+ if ((smp_cpus > 1) && cpu_supports_cps_smp(cpu_type)) {
+ create_cps(s, cpu_type, cbus_irq, i8259_irq);
} else {
- create_cpu_without_cps(cpu_model, cbus_irq, i8259_irq);
+ create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
}
}
@@ -1038,7 +1030,7 @@ void mips_malta_init(MachineState *machine)
}
/* create CPU */
- create_cpu(s, machine->cpu_model, &cbus_irq, &i8259_irq);
+ mips_create_cpu(s, machine->cpu_type, &cbus_irq, &i8259_irq);
/* allocate RAM */
if (ram_size > (2048u << 20)) {
@@ -1264,6 +1256,11 @@ static void mips_malta_machine_init(MachineClass *mc)
mc->block_default_type = IF_IDE;
mc->max_cpus = 16;
mc->is_default = 1;
+#ifdef TARGET_MIPS64
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
+#else
+ mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
+#endif
}
DEFINE_MACHINE("malta", mips_malta_machine_init)