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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-11 11:26:36 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-11 11:26:36 +0000 |
| commit | 8fa7574904793396694fa88834751a93bcdf4e10 (patch) | |
| tree | 71655e2417ee088da62743f4a90da736cbce1e4f /hw/intc/gic_internal.h | |
| parent | 702f6df9602a445103c55ac21af11c7aaedb9b34 (diff) | |
| parent | 69991d7dcbcf7f3fe38274bc67fcba3cbbfda0cf (diff) | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140208' into staging
target-arm queue:
* more A64 Neon instructions
* AArch32 VCVTB and VCVTT ARMv8 instructions
* fixes to inaccuracies in GIC emulation
* libvixl disassembler for A64
* Allwinner SoC ethernet controller
* zynq software system reset support
# gpg: Signature made Sat 08 Feb 2014 15:53:05 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140208: (29 commits)
arm/zynq: Add software system reset via SCLR
hw/arm/allwinner-a10: initialize EMAC
hw/net: add support for Allwinner EMAC Fast Ethernet controller
util/fifo8: clear fifo head upon reset
util/fifo8: implement push/pop of multiple bytes
disas: Implement disassembly output for A64
disas/libvixl: Fix upstream libvixl compilation issues
disas: Add subset of libvixl sources for A64 disassembler
rules.mak: Link with C++ if we have a C++ compiler
rules.mak: Support .cc as a C++ source file suffix
arm_gic: Add GICC_APRn state to the GICState
vmstate: Add uint32 2D-array support
arm_gic: Support setting/getting binary point reg
arm_gic: Keep track of SGI sources
arm_gic: Fix GIC pending behavior
target-arm: Add support for AArch32 64bit VCVTB and VCVTT
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
target-arm: A64: Add 2-reg-misc REV* instructions
target-arm: A64: Add narrowing 2-reg-misc instructions
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc/gic_internal.h')
| -rw-r--r-- | hw/intc/gic_internal.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 8c02d5888c..92a6f7a3ff 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -34,7 +34,6 @@ #define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0) #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm) #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm) -#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0) #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) @@ -63,4 +62,19 @@ void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); +static inline bool gic_test_pending(GICState *s, int irq, int cm) +{ + if (s->revision == REV_NVIC || s->revision == REV_11MPCORE) { + return s->irq_state[irq].pending & cm; + } else { + /* Edge-triggered interrupts are marked pending on a rising edge, but + * level-triggered interrupts are either considered pending when the + * level is active or if software has explicitly written to + * GICD_ISPENDR to set the state pending. + */ + return (s->irq_state[irq].pending & cm) || + (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm)); + } +} + #endif /* !QEMU_ARM_GIC_INTERNAL_H */ |