diff options
| author | Igor Mammedov <imammedo@redhat.com> | 2015-12-28 18:02:49 +0100 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2016-01-09 23:20:19 +0200 |
| commit | 41f95a52004fb5df6b39e0d6322e4a20c4be9e51 (patch) | |
| tree | 24f78d4f5f8ae1c12fe5990cf847f8db11acc664 /hw/i386 | |
| parent | 78e1ad05097a351fe1657713619c8457dfa714da (diff) | |
pc: acpi: q35: move ISA bridge into SSDT
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/i386')
| -rw-r--r-- | hw/i386/acpi-build.c | 54 | ||||
| -rw-r--r-- | hw/i386/q35-acpi-dsdt.dsl | 46 |
2 files changed, 54 insertions, 46 deletions
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index f454ac50e1..103a08f3bd 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1633,8 +1633,21 @@ static void build_piix4_pci0_int(Aml *table) static void build_q35_pci0_int(Aml *table) { + Aml *field; Aml *sb_scope = aml_scope("_SB"); + field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("PRQA", 8)); + aml_append(field, aml_named_field("PRQB", 8)); + aml_append(field, aml_named_field("PRQC", 8)); + aml_append(field, aml_named_field("PRQD", 8)); + aml_append(field, aml_reserved_field(0x20)); + aml_append(field, aml_named_field("PRQE", 8)); + aml_append(field, aml_named_field("PRQF", 8)); + aml_append(field, aml_named_field("PRQG", 8)); + aml_append(field, aml_named_field("PRQH", 8)); + aml_append(sb_scope, field); + aml_append(sb_scope, build_irq_status_method()); aml_append(sb_scope, build_iqcr_method(false)); @@ -1663,6 +1676,46 @@ static void build_q35_pci0_int(Aml *table) aml_append(table, sb_scope); } +static void build_q35_isa_bridge(Aml *table) +{ + Aml *dev; + Aml *scope; + Aml *field; + + scope = aml_scope("_SB.PCI0"); + dev = aml_device("ISA"); + aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000))); + + /* ICH9 PCI to ISA irq remapping */ + aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG, + 0x60, 0x0C)); + + aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG, + 0x80, 0x02)); + field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("COMA", 3)); + aml_append(field, aml_reserved_field(1)); + aml_append(field, aml_named_field("COMB", 3)); + aml_append(field, aml_reserved_field(1)); + aml_append(field, aml_named_field("LPTD", 2)); + aml_append(field, aml_reserved_field(2)); + aml_append(field, aml_named_field("FDCD", 2)); + aml_append(dev, field); + + aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG, + 0x82, 0x02)); + /* enable bits */ + field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE); + aml_append(field, aml_named_field("CAEN", 1)); + aml_append(field, aml_named_field("CBEN", 1)); + aml_append(field, aml_named_field("LPEN", 1)); + aml_append(field, aml_named_field("FDEN", 1)); + aml_append(dev, field); + + aml_append(scope, dev); + aml_append(table, scope); +} + static void build_piix4_pm(Aml *table) { Aml *dev; @@ -1790,6 +1843,7 @@ build_ssdt(GArray *table_data, GArray *linker, build_piix4_pci0_int(ssdt); } else { build_hpet_aml(ssdt); + build_q35_isa_bridge(ssdt); build_isa_devices_aml(ssdt); build_q35_pci0_int(ssdt); } diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl index ec8a48c394..b01d4de6cf 100644 --- a/hw/i386/q35-acpi-dsdt.dsl +++ b/hw/i386/q35-acpi-dsdt.dsl @@ -114,39 +114,6 @@ DefinitionBlock ( } /**************************************************************** - * LPC ISA bridge - ****************************************************************/ - - Scope(\_SB.PCI0) { - /* PCI D31:f0 LPC ISA bridge */ - Device(ISA) { - Name (_ADR, 0x001F0000) // _ADR: Address - - /* ICH9 PCI to ISA irq remapping */ - OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C) - - OperationRegion(LPCD, PCI_Config, 0x80, 0x2) - Field(LPCD, AnyAcc, NoLock, Preserve) { - COMA, 3, - , 1, - COMB, 3, - - Offset(0x01), - LPTD, 2, - , 2, - FDCD, 2 - } - OperationRegion(LPCE, PCI_Config, 0x82, 0x2) - Field(LPCE, AnyAcc, NoLock, Preserve) { - CAEN, 1, - CBEN, 1, - LPEN, 1, - FDEN, 1 - } - } - } - -/**************************************************************** * PCI IRQs ****************************************************************/ @@ -285,19 +252,6 @@ DefinitionBlock ( } } - Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) { - PRQA, 8, - PRQB, 8, - PRQC, 8, - PRQD, 8, - - Offset(0x08), - PRQE, 8, - PRQF, 8, - PRQG, 8, - PRQH, 8 - } - External(LNKA, DeviceObj) External(LNKB, DeviceObj) External(LNKC, DeviceObj) |