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authorPeter Maydell <peter.maydell@linaro.org>2018-04-26 11:56:57 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-04-26 11:56:57 +0100
commit20b2323edf8d42fe024902ca7d847b9f71c98df1 (patch)
tree5659345455e517291d54c7f552c9cd364c208993 /hw/char/serial.c
parent569df5b6e118128995c70d266668f11825c8fec8 (diff)
parentfbf32752663878947de455ff57cb5b9318f14bec (diff)
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180426' into staging
target-arm queue: * xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo * timer/aspeed: fix vmstate version id * hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM * hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' * hw/arm/highbank: don't make sysram 'nomigrate' * hw/arm/raspi: Don't bother setting default_cpu_type * PMU emulation: some minor bugfixes and preparation for support of other events than just the cycle counter * target/arm: Use v7m_stack_read() for reading the frame signature * target/arm: Remove stale TODO comment * arm: always start from first_cpu when registering loader cpu reset callback * device_tree: Increase FDT_MAX_SIZE to 1 MiB # gpg: Signature made Thu 26 Apr 2018 11:46:31 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180426: xilinx_spips: Correct SNOOP_NONE state when flushing the txfifo timer/aspeed: fix vmstate version id hw/arm/aspeed_soc: don't use vmstate_register_ram_global for SRAM hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate' hw/arm/highbank: don't make sysram 'nomigrate' hw/arm/raspi: Don't bother setting default_cpu_type target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide target/arm: Fix bitmask for PMCCFILTR writes target/arm: Allow EL change hooks to do IO target/arm: Add pre-EL change hooks target/arm: Support multiple EL change hooks target/arm: Fetch GICv3 state directly from CPUARMState target/arm: Mask PMU register writes based on PMCR_EL0.N target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0 target/arm: Check PMCNTEN for whether PMCCNTR is enabled target/arm: Use v7m_stack_read() for reading the frame signature target/arm: Remove stale TODO comment arm: always start from first_cpu when registering loader cpu reset callback device_tree: Increase FDT_MAX_SIZE to 1 MiB Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/char/serial.c')
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