diff options
author | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-02 16:48:32 +0000 |
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committer | pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-02 16:48:32 +0000 |
commit | 23e39294034e13d29a0707483542bab850d601b4 (patch) | |
tree | bf8c1fa3e39234083a06bd7b579476f870853b06 /hw/arm_timer.c | |
parent | ab19b0ecfddf94ae2053b973cea5a58c8dac0363 (diff) |
Save/restore for stellaris boards.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4824 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/arm_timer.c')
-rw-r--r-- | hw/arm_timer.c | 49 |
1 files changed, 46 insertions, 3 deletions
diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 540d3dea1b..5150fe9a5a 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -143,6 +143,29 @@ static void arm_timer_tick(void *opaque) arm_timer_update(s); } +static void arm_timer_save(QEMUFile *f, void *opaque) +{ + arm_timer_state *s = (arm_timer_state *)opaque; + qemu_put_be32(f, s->control); + qemu_put_be32(f, s->limit); + qemu_put_be32(f, s->int_level); + qemu_put_ptimer(f, s->timer); +} + +static int arm_timer_load(QEMUFile *f, void *opaque, int version_id) +{ + arm_timer_state *s = (arm_timer_state *)opaque; + + if (version_id != 1) + return -EINVAL; + + s->control = qemu_get_be32(f); + s->limit = qemu_get_be32(f); + s->int_level = qemu_get_be32(f); + qemu_get_ptimer(f, s->timer); + return 0; +} + static void *arm_timer_init(uint32_t freq, qemu_irq irq) { arm_timer_state *s; @@ -155,7 +178,7 @@ static void *arm_timer_init(uint32_t freq, qemu_irq irq) bh = qemu_bh_new(arm_timer_tick, s); s->timer = ptimer_init(bh); - /* ??? Save/restore. */ + register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s); return s; } @@ -218,6 +241,25 @@ static CPUWriteMemoryFunc *sp804_writefn[] = { sp804_write }; +static void sp804_save(QEMUFile *f, void *opaque) +{ + sp804_state *s = (sp804_state *)opaque; + qemu_put_be32(f, s->level[0]); + qemu_put_be32(f, s->level[1]); +} + +static int sp804_load(QEMUFile *f, void *opaque, int version_id) +{ + sp804_state *s = (sp804_state *)opaque; + + if (version_id != 1) + return -EINVAL; + + s->level[0] = qemu_get_be32(f); + s->level[1] = qemu_get_be32(f); + return 0; +} + void sp804_init(uint32_t base, qemu_irq irq) { int iomemtype; @@ -235,7 +277,7 @@ void sp804_init(uint32_t base, qemu_irq irq) iomemtype = cpu_register_io_memory(0, sp804_readfn, sp804_writefn, s); cpu_register_physical_memory(base, 0x00001000, iomemtype); - /* ??? Save/restore. */ + register_savevm("sp804", -1, 1, sp804_save, sp804_load, s); } @@ -303,6 +345,7 @@ void icp_pit_init(uint32_t base, qemu_irq *pic, int irq) iomemtype = cpu_register_io_memory(0, icp_pit_readfn, icp_pit_writefn, s); cpu_register_physical_memory(base, 0x00001000, iomemtype); - /* ??? Save/restore. */ + /* This device has no state to save/restore. The component timers will + save themselves. */ } |