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| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2018-11-02 14:19:12 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-11-02 14:10:53 +0000 |
| commit | b89de436ff63218d31122b2176f7785b0628b3c6 (patch) | |
| tree | dc2a6720ab32385c4c5549494d9044dcd2f98cad /hw/arm/xlnx-versal-virt.c | |
| parent | 0f8d06f16c9d1041d728d09d464462ebe713c662 (diff) | |
hw/arm: versal: Add a model of Xilinx Versal SoC
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20181102131913.1535-2-edgar.iglesias@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-versal-virt.c')
0 files changed, 0 insertions, 0 deletions