diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2013-08-20 14:54:28 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-08-20 14:54:28 +0100 |
| commit | ad666d91f43574fb200c738bc793023ae23d24a5 (patch) | |
| tree | d4153e136d850b5301cb02c2fe47b02addaa598f /hw/arm/exynos4210.c | |
| parent | de3a658f5b1d4ea290cb4369c55e83fdead81933 (diff) | |
hw/arm/exynos4210: Don't use arm_pic_init_cpu()
Drop the now-deprecated arm_pic_init_cpu() in favour of directly
getting the IRQ line from the ARMCPU object.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1375977856-25046-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/arm/exynos4210.c')
| -rw-r--r-- | hw/arm/exynos4210.c | 16 |
1 files changed, 3 insertions, 13 deletions
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 216b9b77d9..4ebb9381b0 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -137,10 +137,8 @@ void exynos4210_write_secondary(ARMCPU *cpu, Exynos4210State *exynos4210_init(MemoryRegion *system_mem, unsigned long ram_size) { - qemu_irq cpu_irq[EXYNOS4210_NCPUS]; int i, n; Exynos4210State *s = g_new(Exynos4210State, 1); - qemu_irq *irqp; qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; unsigned long mem_size; DeviceState *dev; @@ -152,15 +150,6 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, fprintf(stderr, "Unable to find CPU %d definition\n", n); exit(1); } - - /* Create PIC controller for each processor instance */ - irqp = arm_pic_init_cpu(s->cpu[n]); - - /* - * Get GICs gpio_in cpu_irq to connect a combiner to them later. - * Use only IRQ for a while. - */ - cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; } /*** IRQs ***/ @@ -178,8 +167,9 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, } busdev = SYS_BUS_DEVICE(dev); - /* Connect IRQ Gate output to cpu_irq */ - sysbus_connect_irq(busdev, 0, cpu_irq[i]); + /* Connect IRQ Gate output to CPU's IRQ line */ + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ)); } /* Private memory region and Internal GIC */ |