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authorVijai Kumar K <vijai@behindbytes.com>2021-04-12 23:12:48 +0530
committerAlistair Francis <alistair.francis@wdc.com>2021-05-11 20:02:06 +1000
commit0924a423baa227fa8fb363232c20a997cb6f617b (patch)
tree25dd9c3b1c68315221915d7ccfc37546031ad96d /docs
parent65606f21243a796537bfe4708720a9bf4bb50169 (diff)
docs: Add documentation for shakti_c machine
Add documentation for Shakti C reference platform. Signed-off-by: Vijai Kumar K <vijai@behindbytes.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210412174248.8668-1-vijai@behindbytes.com Signed-off-by: Bin Meng <bmeng.cn@gmail.com> [ Changes from Bin Meng: - Add missing TOC Message-id: 20210430070534.1487242-1-bmeng.cn@gmail.com ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'docs')
-rw-r--r--docs/system/riscv/shakti-c.rst82
-rw-r--r--docs/system/target-riscv.rst1
2 files changed, 83 insertions, 0 deletions
diff --git a/docs/system/riscv/shakti-c.rst b/docs/system/riscv/shakti-c.rst
new file mode 100644
index 0000000000..a6035d42b0
--- /dev/null
+++ b/docs/system/riscv/shakti-c.rst
@@ -0,0 +1,82 @@
+Shakti C Reference Platform (``shakti_c``)
+==========================================
+
+Shakti C Reference Platform is a reference platform based on arty a7 100t
+for the Shakti SoC.
+
+Shakti SoC is a SoC based on the Shakti C-class processor core. Shakti C
+is a 64bit RV64GCSUN processor core.
+
+For more details on Shakti SoC, please see:
+https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/README.rst
+
+For more info on the Shakti C-class core, please see:
+https://c-class.readthedocs.io/en/latest/
+
+Supported devices
+-----------------
+
+The ``shakti_c`` machine supports the following devices:
+
+ * 1 C-class core
+ * Core Level Interruptor (CLINT)
+ * Platform-Level Interrupt Controller (PLIC)
+ * 1 UART
+
+Boot options
+------------
+
+The ``shakti_c`` machine can start using the standard -bios
+functionality for loading the baremetal application or opensbi.
+
+Boot the machine
+----------------
+
+Shakti SDK
+~~~~~~~~~~
+Shakti SDK can be used to generate the baremetal example UART applications.
+
+.. code-block:: bash
+
+ $ git clone https://gitlab.com/behindbytes/shakti-sdk.git
+ $ cd shakti-sdk
+ $ make software PROGRAM=loopback TARGET=artix7_100t
+
+Binary would be generated in:
+ software/examples/uart_applns/loopback/output/loopback.shakti
+
+You could also download the precompiled example applicatons using below
+commands.
+
+.. code-block:: bash
+
+ $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
+ $ unzip shakti_sdk_qemu.zip
+
+Then we can run the UART example using:
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M shakti_c -nographic \
+ -bios path/to/shakti_sdk_qemu/loopback.shakti
+
+OpenSBI
+~~~~~~~
+We can also run OpenSBI with Test Payload.
+
+.. code-block:: bash
+
+ $ git clone https://github.com/riscv/opensbi.git -b v0.9
+ $ cd opensbi
+ $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
+ $ export CROSS_COMPILE=riscv64-unknown-elf-
+ $ export FW_FDT_PATH=./shakti.dtb
+ $ make PLATFORM=generic
+
+fw_payload.elf would be generated in build/platform/generic/firmware/fw_payload.elf.
+Boot it using the below qemu command.
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 -M shakti_c -nographic \
+ -bios path/to/fw_payload.elf
diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst
index 8d5946fbbb..4b3c78382c 100644
--- a/docs/system/target-riscv.rst
+++ b/docs/system/target-riscv.rst
@@ -67,6 +67,7 @@ undocumented; you can get a complete list by running
:maxdepth: 1
riscv/microchip-icicle-kit
+ riscv/shakti-c
riscv/sifive_u
RISC-V CPU features