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authorStefan Weil <sw@weilnetz.de>2022-04-22 10:30:07 +0200
committerLaurent Vivier <laurent@vivier.eu>2022-04-26 12:38:44 +0200
commit9b76572431f16dcfb99a826c3df51fcad79fef08 (patch)
treeb9303ed4c7b8cc79c462c76ff240e561d098b28d /docs/pcie_sriov.txt
parenteb5b72c05ef598bf540d4f493093861dae3fdda6 (diff)
docs: Replace Qemu -> QEMU
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Knut Omang <knuto@ifi.uio.no> Message-Id: <20220422083007.1082667-1-sw@weilnetz.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Diffstat (limited to 'docs/pcie_sriov.txt')
-rw-r--r--docs/pcie_sriov.txt6
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/pcie_sriov.txt b/docs/pcie_sriov.txt
index f5e891e1d4..11158dbf88 100644
--- a/docs/pcie_sriov.txt
+++ b/docs/pcie_sriov.txt
@@ -8,8 +8,8 @@ of a PCI Express device. It allows a single physical function (PF) to appear as
virtual functions (VFs) for the main purpose of eliminating software
overhead in I/O from virtual machines.
-Qemu now implements the basic common functionality to enable an emulated device
-to support SR/IOV. Yet no fully implemented devices exists in Qemu, but a
+QEMU now implements the basic common functionality to enable an emulated device
+to support SR/IOV. Yet no fully implemented devices exists in QEMU, but a
proof-of-concept hack of the Intel igb can be found here:
git://github.com/knuto/qemu.git sriov_patches_v5
@@ -18,7 +18,7 @@ Implementation
==============
Implementing emulation of an SR/IOV capable device typically consists of
implementing support for two types of device classes; the "normal" physical device
-(PF) and the virtual device (VF). From Qemu's perspective, the VFs are just
+(PF) and the virtual device (VF). From QEMU's perspective, the VFs are just
like other devices, except that some of their properties are derived from
the PF.