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authorChristoph Müllner <christoph.muellner@vrull.eu>2023-06-12 13:10:33 +0200
committerAlistair Francis <alistair.francis@wdc.com>2023-07-10 22:29:14 +1000
commitf6f72338d80ec6f15a6b18643797bc10901aadf3 (patch)
tree177d8d276aa4dd93393fcce5b8268db4878b5762 /disas/riscv-xventana.h
parentc859a2424dbbae8f5ea64c0f8445981402cd8552 (diff)
disas/riscv: Add support for XVentanaCondOps
This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'disas/riscv-xventana.h')
-rw-r--r--disas/riscv-xventana.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/disas/riscv-xventana.h b/disas/riscv-xventana.h
new file mode 100644
index 0000000000..72be9ffa16
--- /dev/null
+++ b/disas/riscv-xventana.h
@@ -0,0 +1,18 @@
+/*
+ * QEMU disassembler -- RISC-V specific header (xventana*).
+ *
+ * Copyright (c) 2023 VRULL GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef DISAS_RISCV_XVENTANA_H
+#define DISAS_RISCV_XVENTANA_H
+
+#include "disas/riscv.h"
+
+extern const rv_opcode_data ventana_opcode_data[];
+
+void decode_xventanacondops(rv_decode*, rv_isa);
+
+#endif /* DISAS_RISCV_XVENTANA_H */