diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-16 19:02:21 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-16 19:02:21 +0100 |
| commit | b8f7ff1e10b4d03555d6a5da011c2aae10063ab8 (patch) | |
| tree | cbd691dccf09a4dad1d35938d3e70efd385a8dc8 /MAINTAINERS | |
| parent | bb16c0412a572c2c9cd44496deb3ad430bc49c1a (diff) | |
| parent | 8639c5c95472ee79391a7e7826d1af23948b71f6 (diff) | |
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' into staging
MIPS queue Aug 16, 2018
# gpg: Signature made Thu 16 Aug 2018 18:19:36 BST
# gpg: using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65
* remotes/amarkovic/tags/mips-queue-aug-2018:
qemu-doc: Amend MIPS-related items
linux-user: Add preprocessor availability control to some syscalls
linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
elf: Add ELF flags for MIPS machine variants
elf: Remove duplicate preprocessor constant definition
target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
target/mips: Don't update BadVAddr register in Debug Mode
target/mips: Implement CP0 Config1.WR bit functionality
target/mips: Add CP0 BadInstrX register
target/mips: Update some CP0 registers bit definitions
target/mips: Fix two instances of shadow variables
target/mips: Mark switch fallthroughs with interpretable comments
target/mips: Avoid case statements formulated by ranges - part 2
target/mips: Avoid case statements formulated by ranges - part 1
MAINTAINERS: Update target/mips maintainer's email addresses
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index c48d9271cf..272a534ca0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -187,7 +187,7 @@ F: disas/microblaze.c MIPS M: Aurelien Jarno <aurelien@aurel32.net> -M: Aleksandar Markovic <aleksandar.markovic@mips.com> +M: Aleksandar Markovic <amarkovic@wavecomp.com> S: Maintained F: target/mips/ F: hw/mips/ @@ -718,7 +718,7 @@ S: Maintained F: hw/mips/mips_malta.c Mipssim -M: Aleksandar Markovic <aleksandar.markovic@mips.com> +M: Aleksandar Markovic <amarkovic@wavecomp.com> S: Odd Fixes F: hw/mips/mips_mipssim.c F: hw/net/mipsnet.c @@ -729,14 +729,15 @@ S: Maintained F: hw/mips/mips_r4k.c Fulong 2E -M: Aleksandar Markovic <aleksandar.markovic@mips.com> +M: Aleksandar Markovic <amarkovic@wavecomp.com> S: Odd Fixes F: hw/mips/mips_fulong2e.c F: hw/isa/vt82c686.c + F: include/hw/isa/vt82c686.h Boston -M: Paul Burton <paul.burton@mips.com> +M: Paul Burton <pburton@wavecomp.com> S: Maintained F: hw/core/loader-fit.c F: hw/mips/boston.c |