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| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2013-04-03 14:04:09 +1000 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-04-04 00:55:03 +0200 |
| commit | 4dbb9ed3263e0f48282a2fc3d05099ba63e5b0e2 (patch) | |
| tree | 8a1dec9e8e14b07e0856ddb5f4a03339b2389943 | |
| parent | bd4a47330ed5b9661205dd4ac2023e452b856bf9 (diff) | |
xilinx_axienet: pump events as appropriate
When the conditions blocking receiving are cleared, check for buffered rx
packets.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
| -rw-r--r-- | hw/xilinx_axienet.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index 5785290224..07c4badd98 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr, s->rcw[addr & 1] = value; if ((addr & 1) && value & RCW1_RST) { axienet_rx_reset(s); + } else { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); } break; |