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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2013-12-13 16:28:52 +1000
committerEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-02-11 22:57:44 +1000
commit2a221651949a8dcf74faa0989d7b0dda96a76911 (patch)
tree5fddb49fd96221b47b158828b620ee8e413c10e1
parentdb3be60deb01af6ee72edc7fa13f0ff820029831 (diff)
exec: Make cpu_physical_memory_write_rom input an AS
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--exec.c15
-rw-r--r--hw/core/loader.c3
-rw-r--r--hw/intc/apic.c3
-rw-r--r--hw/sparc/sun4m.c3
-rw-r--r--include/exec/cpu-common.h2
5 files changed, 15 insertions, 11 deletions
diff --git a/exec.c b/exec.c
index 2e2fbd8dca..1e99115abc 100644
--- a/exec.c
+++ b/exec.c
@@ -2102,7 +2102,7 @@ enum write_rom_type {
FLUSH_CACHE,
};
-static inline void cpu_physical_memory_write_rom_internal(
+static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
hwaddr addr, const uint8_t *buf, int len, enum write_rom_type type)
{
hwaddr l;
@@ -2112,8 +2112,7 @@ static inline void cpu_physical_memory_write_rom_internal(
while (len > 0) {
l = len;
- mr = address_space_translate(&address_space_memory,
- addr, &addr1, &l, true);
+ mr = address_space_translate(as, addr, &addr1, &l, true);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -2139,10 +2138,10 @@ static inline void cpu_physical_memory_write_rom_internal(
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len)
{
- cpu_physical_memory_write_rom_internal(addr, buf, len, WRITE_DATA);
+ cpu_physical_memory_write_rom_internal(as, addr, buf, len, WRITE_DATA);
}
void cpu_flush_icache_range(hwaddr start, int len)
@@ -2157,7 +2156,8 @@ void cpu_flush_icache_range(hwaddr start, int len)
return;
}
- cpu_physical_memory_write_rom_internal(start, NULL, len, FLUSH_CACHE);
+ cpu_physical_memory_write_rom_internal(&address_space_memory,
+ start, NULL, len, FLUSH_CACHE);
}
typedef struct {
@@ -2721,7 +2721,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
l = len;
phys_addr += (addr & ~TARGET_PAGE_MASK);
if (is_write)
- cpu_physical_memory_write_rom(phys_addr, buf, l);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ phys_addr, buf, l);
else
cpu_physical_memory_rw(phys_addr, buf, l, is_write);
len -= l;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 0634bee20c..e1c3f3a860 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -778,7 +778,8 @@ static void rom_reset(void *unused)
void *host = memory_region_get_ram_ptr(rom->mr);
memcpy(host, rom->data, rom->datasize);
} else {
- cpu_physical_memory_write_rom(rom->addr, rom->data, rom->datasize);
+ cpu_physical_memory_write_rom(&address_space_memory,
+ rom->addr, rom->data, rom->datasize);
}
if (rom->isrom) {
/* rom needs to be written only once */
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 3d3deb6298..361ae90b65 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -129,7 +129,8 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
}
vapic_state.irr = vector & 0xff;
- cpu_physical_memory_write_rom(s->vapic_paddr + start,
+ cpu_physical_memory_write_rom(&address_space_memory,
+ s->vapic_paddr + start,
((void *)&vapic_state) + start, length);
}
}
diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c
index 94f79508d8..2957d90177 100644
--- a/hw/sparc/sun4m.c
+++ b/hw/sparc/sun4m.c
@@ -577,7 +577,8 @@ static void idreg_init(hwaddr addr)
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, addr);
- cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
+ cpu_physical_memory_write_rom(&address_space_memory,
+ addr, idreg_data, sizeof(idreg_data));
}
#define MACIO_ID_REGISTER(obj) \
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d0fe123677..a21b65a893 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -108,7 +108,7 @@ void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(hwaddr addr,
+void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
const uint8_t *buf, int len);
void cpu_flush_icache_range(hwaddr start, int len);