diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-02 13:04:27 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-02-08 09:58:24 +0100 |
| commit | 48bffe7f6b65e78d84ffae0e4385af1aa935767c (patch) | |
| tree | 97a9b92e47b36b1e7fc79523ea7388fee5daeff6 | |
| parent | fa581531ffdc94ba18da6ec0c566bece57a60a85 (diff) | |
target/tricore: Fix RRPW_DEXTR
if we used const16 == 0 we would crash qemu with the error:
../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed
This whole instruction can be handled by 'tcg_gen_extract2_tl' which
takes care of this special case as well.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-6-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| -rw-r--r-- | target/tricore/translate.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6149d4f5c0..3b4ec530b1 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8706,15 +8706,9 @@ static void decode_32Bit_opc(DisasContext *ctx) r2 = MASK_OP_RRPW_S2(ctx->opcode); r3 = MASK_OP_RRPW_D(ctx->opcode); const16 = MASK_OP_RRPW_POS(ctx->opcode); - if (r1 == r2) { - tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); - } else { - temp = tcg_temp_new(); - tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); - tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); - tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); - tcg_temp_free(temp); - } + + tcg_gen_extract2_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], cpu_gpr_d[r1], + 32 - const16); break; /* RRR Format */ case OPCM_32_RRR_COND_SELECT: |