diff options
| author | Kito Cheng <kito.cheng@sifive.com> | 2021-07-06 11:50:15 +0800 |
|---|---|---|
| committer | Laurent Vivier <laurent@vivier.eu> | 2021-07-07 21:14:47 +0200 |
| commit | cb46938c45144045c1ae278abb05b6a1cf2de445 (patch) | |
| tree | d13cfd8b9c2c50ed179cda69f38e031140943669 | |
| parent | 9aef0954195cc592e86846dbbe7f3c2c5603690a (diff) | |
linux-user/elfload: Implement ELF_HWCAP for RISC-V
Set I, M, A, F, D and C bit for hwcap if misa is set.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210706035015.122899-1-kito.cheng@sifive.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| -rw-r--r-- | linux-user/elfload.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 598ab8aa13..42ef2a1148 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #define ELF_CLASS ELFCLASS64 #endif +#define ELF_HWCAP get_elf_hwcap() + +static uint32_t get_elf_hwcap(void) +{ +#define MISA_BIT(EXT) (1 << (EXT - 'A')) + RISCVCPU *cpu = RISCV_CPU(thread_cpu); + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + + return cpu->env.misa & mask; +#undef MISA_BIT +} + static inline void init_thread(struct target_pt_regs *regs, struct image_info *infop) { |