diff options
author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-26 10:46:39 +0000 |
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committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2005-11-26 10:46:39 +0000 |
commit | 9332f9dafa33b085488a5369333213d549dbdc7f (patch) | |
tree | 4f1cfad1613e5ccfd798a7406ead9601310e8f41 | |
parent | e8ebb8a8d7d10bd04eab9ae8ad3da707d178a02d (diff) |
ARM CPU suspend/halt (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1663 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | cpu-exec.c | 11 | ||||
-rw-r--r-- | target-arm/cpu.h | 2 | ||||
-rw-r--r-- | target-arm/op.c | 7 | ||||
-rw-r--r-- | target-arm/translate.c | 9 |
4 files changed, 28 insertions, 1 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index f411eccf81..cddea532a4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -274,6 +274,17 @@ int cpu_exec(CPUState *env1) return EXCP_HALTED; } } +#elif defined(TARGET_ARM) + if (env1->halted) { + /* An interrupt wakes the CPU even if the I and F CPSR bits are + set. */ + if (env1->interrupt_request + & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) { + env1->halted = 0; + } else { + return EXCP_HALTED; + } + } #endif cpu_single_env = env1; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 1c1233c198..3b36839e4b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -90,7 +90,7 @@ typedef struct CPUARMState { int exception_index; int interrupt_request; int user_mode_only; - uint32_t address; + int halted; /* VFP coprocessor state. */ struct { diff --git a/target-arm/op.c b/target-arm/op.c index 09449f28e4..35419a1b71 100644 --- a/target-arm/op.c +++ b/target-arm/op.c @@ -878,6 +878,13 @@ void OPPROTO op_debug(void) cpu_loop_exit(); } +void OPPROTO op_wfi(void) +{ + env->exception_index = EXCP_HLT; + env->halted = 1; + cpu_loop_exit(); +} + /* VFP support. We follow the convention used for VFP instrunctions: Single precition routines have a "s" suffix, double precision a "d" suffix. */ diff --git a/target-arm/translate.c b/target-arm/translate.c index 8df10bebc8..930826cab9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -496,6 +496,15 @@ static int disas_cp15_insn(DisasContext *s, uint32_t insn) if (IS_USER(s)) { return 1; } + if ((insn & 0x0fff0fff) == 0x0e070f90 + || (insn & 0x0fff0fff) == 0x0e070f58) { + /* Wait for interrupt. */ + gen_op_movl_T0_im((long)s->pc); + gen_op_movl_reg_TN[0][15](); + gen_op_wfi(); + s->is_jmp = DISAS_JUMP; + return 0; + } rd = (insn >> 12) & 0xf; if (insn & (1 << 20)) { gen_op_movl_T0_cp15(insn); |