diff options
| author | Michael S. Tsirkin <mst@redhat.com> | 2019-07-11 15:24:18 -0400 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2019-07-12 10:56:26 -0400 |
| commit | 8e2e95ef04a8d40d59d1d735e3ebd48324c27417 (patch) | |
| tree | 1511c527059640124ed7e6b8dbbce13bf2982553 | |
| parent | a2a9d4adabe340617a24eb73a8b2a116d28a6b38 (diff) | |
xio3130_downstream: typo fix
slt ctl/status are passed in incorrect order.
Fix this up.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
| -rw-r--r-- | hw/pci-bridge/xio3130_downstream.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 899b0fd6c9..182e164f74 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -43,7 +43,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, { uint16_t slt_ctl, slt_sta; - pcie_cap_slot_get(d, &slt_sta, &slt_ctl); + pcie_cap_slot_get(d, &slt_ctl, &slt_sta); pci_bridge_write_config(d, address, val, len); pcie_cap_flr_write_config(d, address, val, len); pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); |