diff options
| author | Richard Henderson <rth@twiddle.net> | 2016-11-16 11:37:15 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:11 -0800 |
| commit | 0efa8208544e3e5984d7089ec751d3fbcfd43156 (patch) | |
| tree | 51f4914944b234cf9124aa9a4a4d050af2192ddc | |
| parent | c3aa369e5d895b4a48339fd3dbb3f72228a8ecc9 (diff) | |
target-tricore: Use clz opcode
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target/tricore/helper.h | 2 | ||||
| -rw-r--r-- | target/tricore/op_helper.c | 10 | ||||
| -rw-r--r-- | target/tricore/translate.c | 5 |
3 files changed, 3 insertions, 14 deletions
diff --git a/target/tricore/helper.h b/target/tricore/helper.h index 9333e161ab..2cf04e1b11 100644 --- a/target/tricore/helper.h +++ b/target/tricore/helper.h @@ -87,9 +87,7 @@ DEF_HELPER_FLAGS_2(min_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_2(ixmin, TCG_CALL_NO_RWG_SE, i64, i64, i32) DEF_HELPER_FLAGS_2(ixmin_u, TCG_CALL_NO_RWG_SE, i64, i64, i32) /* count leading ... */ -DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32) -DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(cls, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index ac02e0a36b..3731d5e6f1 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -1733,11 +1733,6 @@ EXTREMA_H_B(min, <) #undef EXTREMA_H_B -uint32_t helper_clo(target_ulong r1) -{ - return clo32(r1); -} - uint32_t helper_clo_h(target_ulong r1) { uint32_t ret_hw0 = extract32(r1, 0, 16); @@ -1756,11 +1751,6 @@ uint32_t helper_clo_h(target_ulong r1) return ret_hw0 | (ret_hw1 << 16); } -uint32_t helper_clz(target_ulong r1) -{ - return clz32(r1); -} - uint32_t helper_clz_h(target_ulong r1) { uint32_t ret_hw0 = extract32(r1, 0, 16); diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 36f734a662..69cdfb9177 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6367,7 +6367,8 @@ static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_CLO: - gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); break; case OPC2_32_RR_CLO_H: gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); @@ -6379,7 +6380,7 @@ static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); break; case OPC2_32_RR_CLZ: - gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); break; case OPC2_32_RR_CLZ_H: gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); |