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authorFabien Chouteau <chouteau@adacore.com>2013-06-18 16:53:01 +0200
committerAlexander Graf <agraf@suse.de>2013-07-01 01:11:17 +0200
commitb177d8b77c7301da9b51b829b0edcff367e92023 (patch)
treea63f298bc2476849c9757dd48c8ed2ebc0debcc5
parent886b75779104f38c30cc2594fcf2b214615a242d (diff)
PPC: Fix GDB read on code area for PPC6xx
On PPC 6xx, data and code have separated TLBs. Until now QEMU was only looking at data TLBs, which is not good when GDB wants to read code. This patch adds a second call to get_physical_address() with an ACCESS_CODE type of access when the first call with ACCESS_INT fails. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--target-ppc/mmu_helper.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 34330dc7d6..385b67ab23 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1431,7 +1431,15 @@ hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
}
if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) {
- return -1;
+
+ /* Some MMUs have separate TLBs for code and data. If we only try an
+ * ACCESS_INT, we may not be able to read instructions mapped by code
+ * TLBs, so we also try a ACCESS_CODE.
+ */
+ if (unlikely(get_physical_address(env, &ctx, addr, 0,
+ ACCESS_CODE) != 0)) {
+ return -1;
+ }
}
return ctx.raddr & TARGET_PAGE_MASK;