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authorRichard Henderson <rth@twiddle.net>2011-05-04 13:34:30 -0700
committerBlue Swirl <blauwirbel@gmail.com>2011-05-08 16:55:23 +0000
commit00a152b48b0b7d9d77842511afcf59b5f25ec554 (patch)
treee625c6703bbdb3b23e64acb58b189d34280fc32c
parent403946c009cc7fd8a8aa719236801ed12121f8fd (diff)
target-i386: Privatize some i386-specific interrupt names.
SMI, VIRQ, INIT, SIPI, and MCE are all only used by the i386 port. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--cpu-all.h5
-rw-r--r--poison.h2
-rw-r--r--target-i386/cpu.h8
3 files changed, 8 insertions, 7 deletions
diff --git a/cpu-all.h b/cpu-all.h
index b1305dbbf4..39dfa464ba 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -828,12 +828,7 @@ extern CPUState *cpu_single_env;
/* Temporary remapping from the generic names back to the previous
cpu-specific names. These will be moved to target-foo/cpu.h next. */
-#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
-#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
-#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
-#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
-#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
/* The set of all bits that should be masked when single-stepping. */
#define CPU_INTERRUPT_SSTEP_MASK \
diff --git a/poison.h b/poison.h
index 787f8e9aab..4fcf46dcf1 100644
--- a/poison.h
+++ b/poison.h
@@ -40,9 +40,7 @@
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
#pragma GCC poison CPU_INTERRUPT_HALT
-#pragma GCC poison CPU_INTERRUPT_SMI
#pragma GCC poison CPU_INTERRUPT_DEBUG
-#pragma GCC poison CPU_INTERRUPT_VIRQ
#pragma GCC poison CPU_INTERRUPT_NMI
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0
#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c7047d5912..1fc421f6ac 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -466,6 +466,14 @@
#define EXCP_SYSCALL 0x100 /* only happens in user only emulation
for syscall instruction */
+/* i386-specific interrupt pending bits. */
+#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
+#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
+#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
+#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
+#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
+
+
enum {
CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */