diff options
| author | Alistair Francis <alistair.francis@xilinx.com> | 2015-05-29 16:30:43 +1000 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2015-06-21 17:20:15 +1000 |
| commit | 9aaaa181949e4a23ca298fb7006e2d8bac842e92 (patch) | |
| tree | aa9dd2fd75c9f98e80950fc56bba2902550854bd | |
| parent | 8bac22423e4c3b70082dd6c1b492ccf21f3b5a0c (diff) | |
target-microblaze: Allow the stack protection to be disabled
Microblaze stack protection is configurable and isn't always enabled.
This patch allows the stack protection to be disabled from the
CPU properties.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target-microblaze/cpu-qom.h | 5 | ||||
| -rw-r--r-- | target-microblaze/cpu.c | 5 | ||||
| -rw-r--r-- | target-microblaze/cpu.h | 1 | ||||
| -rw-r--r-- | target-microblaze/translate.c | 4 |
4 files changed, 13 insertions, 2 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index e3e070159f..e08adb9e02 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -59,6 +59,11 @@ typedef struct MicroBlazeCPU { uint32_t base_vectors; /*< public >*/ + /* Microblaze Configuration Settings */ + struct { + bool stackprot; + } cfg; + CPUMBState env; } MicroBlazeCPU; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 95be540124..d3dad4ab7a 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -114,6 +114,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_USE_FPU2_MASK \ | PVR2_FPU_EXC_MASK \ | 0; + + env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0; + env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); @@ -156,6 +159,8 @@ static const VMStateDescription vmstate_mb_cpu = { static Property mb_properties[] = { DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), + DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, + true), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 534e1cf6a5..60a7500b80 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -128,6 +128,7 @@ typedef struct CPUMBState CPUMBState; #define PVR0_FAULT 0x00100000 #define PVR0_VERSION_MASK 0x0000FF00 #define PVR0_USER1_MASK 0x000000FF +#define PVR0_SPROT_MASK 0x00000001 /* User 2 PVR mask */ #define PVR1_USER2_MASK 0xFFFFFFFF diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 4068946f40..bd10b40000 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -862,7 +862,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) int stackprot = 0; /* All load/stores use ra. */ - if (dc->ra == 1) { + if (dc->ra == 1 && dc->cpu->cfg.stackprot) { stackprot = 1; } @@ -875,7 +875,7 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) return &cpu_R[dc->ra]; } - if (dc->rb == 1) { + if (dc->rb == 1 && dc->cpu->cfg.stackprot) { stackprot = 1; } |