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authorCao Jiaxi <driver1998@foxmail.com>2019-05-07 12:55:03 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-05-07 12:55:03 +0100
commit8041336ef74e19ca607c1601016333c986de8f9c (patch)
tree7b96f96d95f2192144835ba042de5e94925091a9
parent8ac65578920a98a845aa8c80ea19140a51440185 (diff)
util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
Windows ARM64 uses LLP64 model, which breaks current assumptions. Signed-off-by: Cao Jiaxi <driver1998@foxmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20190503003707.10185-1-driver1998@foxmail.com Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--util/cacheinfo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index 3cd080b83d..eebe1ce9c5 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -107,7 +107,7 @@ static void sys_cache_info(int *isize, int *dsize)
static void arch_cache_info(int *isize, int *dsize)
{
if (*isize == 0 || *dsize == 0) {
- unsigned long ctr;
+ uint64_t ctr;
/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
but (at least under Linux) these are marked protected by the