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author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-13 02:21:28 +0000 |
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committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-09-13 02:21:28 +0000 |
commit | d8134d91d9b7f9f1c7cd0d8acf33df2c25629907 (patch) | |
tree | fb3e855dcd598ee499947a8847310125252f1929 | |
parent | d14049eaec8d9c4349ae21eb276b70de995fdf68 (diff) |
Intel cache info, by Filip Navara.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3162 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r-- | target-i386/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target-i386/helper.c b/target-i386/helper.c index 3c051b9ea3..64c3a61325 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1657,10 +1657,10 @@ void helper_cpuid(void) break; case 2: /* cache info: needed for Pentium Pro compatibility */ - EAX = 0x410601; + EAX = 1; EBX = 0; ECX = 0; - EDX = 0; + EDX = 0x2c307d; break; case 0x80000000: EAX = env->cpuid_xlevel; |